Method and arrangement for changing parallel clock signals in a digital data transmission

ABSTRACT

A changeover arrangement for the clock signals of parallel transmission connections of an assured data transmission link, wherein a clock signal is sent for the transmission paths by parallel outdoor units (OU) located in succession to a common indoor unit (IU), the clock signal is received by a corresponding set of second outdoor units, where phase locked loop signals are used to achieve the lock to the signal, and subsequent to which a second IU receives information of the mode of the phase lock. In addition, when errors are caused in the employed connection, the receiving unit selects a transmission path that has fewer errors based on mode information obtained from the outdoor unit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a U.S. national stage of application No. PCT/F100/00279, filedon Mar. 31, 2000. Priority is claimed on the following applicationCountry: Finland, Application No.: 990738, Filed: Apr. 1, 1999.

BACKGROUND OF THE INVENTION

The invention relates to a method and arrangement for changing parallelclock signals in the propagation assurance of digital data transmission,particularly for realising the propagation assurance of radio links. Theinvention is suited to other data transmission connections as well, forinstance to connections using optical transmission paths.

The quality requirements for a digital radio link are generally known;said requirements are set for example by the ITU, InternationalTelecommunication Union. The quality requirements refer to thereliability and interference-free quality of the transmission. The mostimportant features are usability, error ratio and phase noise. Among thefactors that affect the fulfilment of said criteria are hardwaremalfunctions, weather and changes in the signal path. In order to fulfilthe requirements, it is necessary to provide an equipment andpropagation assurance for the radio link, which means the use ofalternative equipment and transmission paths. By means of equipmentassurance, there is obtained a more reliable usability, and bypropagation assurance, there is obtained both a lower error ratio and alower phase noise.

FIG. 1 is a block diagram illustrating one target of propagationassurance. A public switched telephone network (PSTN) 11 is connected bywires to a mobile switching centre (MSC) 12. The security of the radiolink between the switching centre 12 and the base station controller(BSC) 13 is extremely important, wherefore it is generally assured. Thecontroller 13 is further connected, by radio connections which can alsobe backed up, to base telecommunication stations (BTS) 14, 16, 18 and totheir antennas 15, 17, 19.

The propagation assurance of radio links is realised by means of one orseveral parallel radio connections. Now in parallel with the major radioconnection, there is constructed one or several other backuptransmission paths that carry the same information. The transmissionpaths are preferably different in order to prevent possible interferencecaused by the terrain and/or weather changes from affecting both pathsat the same time. Among the transmission paths, there is selected theone that has, in the prevailing conditions, a better signal at thestation receiving the radio link. The applied criterion for theselection is generally the signal strength, but also the correctness ofthe parity of the received information. The changing of the transmissionpath is carried out by means of a specific changeover device, in a waythat is as error-free as possible, by compensating both the dynamic andstatic phase differences caused by the propagation of the signals indifferent transmission paths. The block dealing with the clock signal isthe most critical part in the changeover device.

Among the drawbacks with known analog arrangements for changing theclock signal are the required separate components; in order to be ableto use them, there is needed space on the circuit board and they consumea remarkable amount of power.

Another drawback with known analog arrangements is their cumbersometuning as a final step in the production.

SUMMARY OF THE INVENTION

The object of the invention is to introduce an advanced method andarrangement for changing the clock signals in parallel transmissionconnections of a assured data transmission link. According to the methodof the invention, the receiving transmission path is changed prior tolosing the phase lock, and the data transmission of the link remainserror-free, in case at least one of the transmission paths transmits theclock signal as sufficiently free of errors, even if errors should occurin another path.

This is realised so that through the parallel outdoor units (OU),located in succession to the common indoor unit (IU), there is sent aclock signal to the transmission paths, said clock signal is received bya second set of outdoor units, where the signal is locked by phaselocked loops, and information of the mode of the phase lock istransmitted to the second indoor unit; further, there is chosen, in thereceiving indoor unit, on the basis of the information obtained from theoutdoor unit, a transmission path that contains less errors, in caseerrors occur with the employed connection. Here also a fading of theclock signal, leading to a disconnection from the phase lock, isconsidered as an error.

The invention relates to a method for changing parallel clock signals indigital data transmission. According to the invention, the changing ofthe clock signals is requested from the changeover device by a controlsignal based on a signal indicating an uncertainty in the locking,obtained from the phase locked loop; then there is expected asimultaneous signal pattern “11”, i.e. an identical mode in order to getthe signals in the same active part of the phase, as well as a turningin the polarity of the signal phase difference, in order to obtain asituation where the signals have just recently been either in the samephase or in a phase shift of 180°, and after a delay DL, the clocksignals are changed at a moment during which the clock signals inquestion are as near to phase coincidence as possible.

The invention relates to an indoor unit provided for digital datatransmission and for changing the clock signal to be received amongparallel clock signals of digital data transmission. According to theinvention, the indoor unit includes an changeover device in order toreceive and change a propagation assured clock signal on the basis ofmissing the locking.

The invention also relates to an outdoor unit provided for digital datatransmission and for changing the parallel clock signals of digital datatransmission. According to the invention, the outdoor unit includes atransmitter for transmitting the clock signal and respectively areceiver for receiving the clock signal, a phase lock synchronised withthe received clock signal and further a signal output for indicating themode of the synchronisation for the indoor unit.

The invention relates to an arrangement for changing parallel clocksignals in digital data transmission, said arrangement comprising afirst indoor unit for dividing the clock signals to be transmitted,antennas for transmitting and receiving parallel clock signals, andanother indoor unit for selecting the clock signals to be received.According to the invention, it also comprises

a first changeover device in the first indoor unit and a secondchangeover device in the second indoor unit in order to receive thepropagation assured clock signal;

in the transmission paths, a first and second outdoor unit in thetransmitter transmitting the clock signal, and respectively in thereceiver receiving the clock signal, as well as a phase lock which issynchronised with the received clock signal.

According to the invention, the changing of the transmission path iscarried out always when the reception of the clock signal deterioratesto the extent that the loop that is phase locked to the clock signaldoes not keep in phase.

The changeover device can be realised with a fully application specificintegrated circuit (ASIC).

An advantage of the invention is a shorter mean time between failure(MTBF) owing to a smaller number of components.

Preferred embodiments of the invention are set forth in the independentclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described in more detail below, with reference to theaccompanying drawings, where

FIG. 1 is a block diagram illustrating a service environment accordingto the invention,

FIG. 2 is a flow diagram illustrating a method according to theinvention,

FIG. 3 is a block diagram illustrating a link arrangement according tothe invention,

FIG. 4 is a block diagram illustrating a known signal changeover device,

FIG. 5 is a block diagram illustrating a changeover device applying aclock signal multiplexer according to the invention,

FIG. 6 is a block diagram illustrating a clock signal multiplexeraccording to the invention,

FIG. 7 is a block diagram illustrating another clock signal multiplexeraccording to the invention, and

FIG. 8 is a block diagram illustrating a third clock signal multiplexeraccording to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 was already dealt with above, in the description of the priorart.

The flow diagram of FIG. 2 illustrates the operation steps of a methodaccording to the invention. The data flow to be transmitted is dividedinto two transmissions, and there is chosen a primary transmission path,i.e. a default path 21. The clock signal is transmitted, 22, throughboth transmission paths, for instance via a radio connection. Whenreceiving the clock signals, the operational reliability of the loopthat is phase locked to the clock signal is detected, 23, on bothtransmission paths. If the operational reliability of the phase lockedloop is sufficient, the phase lock of the clock signal in the chosentransmission path is used, 26. If the operational reliability of thephase locked loop is not sufficient, 24, the chosen transmission path ofthe clock signal is changed, 25, by changing over to the phase lockwhich is locked in the clock signal of the other transmission path.However, the clock signal is transmitted through both transmissionpaths.

FIG. 3 is a block diagram illustrating the essential elements of a linkarrangement according to the invention. An indoor unit (IU) 31 comprisesa changeover device (CD) 32 for receiving propagation assuredinformation. The first transmission path comprises an outdoor unit (OU)OU1 33, antennas 34, 35 and an outdoor unit OU1 36. On the right-handside, there is shown an indoor unit IU 37 that is common for bothtransmission paths, and a changeover device CD 38 included in saidindoor unit 37. The other transmission path comprises correspondingdevices 39, 40, 41, 42. The selection of the transmission path fortransmissions from left to right is carried out by the changeover device38, and the selection of the transmission path for transmissions fromright to left is carried out by the changeover device 32. The outdoorunits 33, 36, 39, 42 comprise means 33A, 36A, 39A, 42A for creating andoutputting the signal that indicates the mode of the synchronisation inthe clock signal reception.

FIG. 4 illustrates a prior art changeover device where the pairs of twoclock signals CLK and a data signals DATA are changed. The elementsoutlined by the dotted line 41 are realised by an application specificintegrated circuit (ASIC), and they include the following parts: anelastic buffer ELASTIC BUFFER 1 receiving the first signal pair CLK1,DATA1, an elastic buffer ELASTIC BUFFER 2 receiving the second signalpair CLK2, DATA2, a multiplexer REF MUX 44 of the reference clocksignal, as well as a correlator and multiplexer CORR & MUX 47. Outsidethe integrated circuit, there are needed at least an analog low passfilter (LPF) 45 and a voltage controlled oscillator (VCO) 46. Thedifference in the write and read addresses of the active buffer 42 or 43is conducted, via the multiplexer REF MUX 44, to the filter 45 in orderto control the voltage controlled oscillator 46.

The writing to buffers is synchronised with incoming clock signals CLK1,CLK2, and the reading is synchronised by the output signal CLK of thevoltage controlled oscillator 46, which signal is locked to the clocksignal CLK1 or CLK2 of the active cable by the signal of the timedifference between writing and reading the information, which signal isobtained from the buffer. The cable to be received is determined in thecorrelator 47, and there are created control signals CONTROL1, 2 forreading the buffers and a control signal CONTROL3 for controlling themultiplexer.

FIG. 5 represents a block diagram of a signal changeover deviceaccording to the invention in an application specific integratedcircuit. The clock signals CLK1, CLK2 of the received signal pairs areconducted to the clock signal multiplexer CLK MUX 51, where the clocksignal to be received is selected. Both the clock signals CLK1, CLK2 andthe data signals DATA1, 2 are also conducted to the data frame decodingblocks 52, 53, where the signals are used to create for example thefollowing signals: synchronising signal SYNC, bit error signal (BE),frame alignment alarm signal (FAA), and pseudo frame signal (PF), aswell as the data signals DATADF1, DATADF2 decoded from the frames. Theoutdoor unit OU activates the PF signal while loosing the locking of theclock signal CLK1, CLK2 to be received. In that case the data signal tobe transmitted is replaced by a predetermined frame structure. The PFsignal is used to indicate, prior to the FAA signal, an error situationin the reception of the clock signal CLK1, CLK2 in the indoor unit, andthe FAA signal is only activated on the basis of several alignmenterrors in received frames. Owing to the pseudo frame structure, the datatransmission between the outdoor unit OU and the indoor unit IU can bekept in operation even if the outdoor unit does not receive a properclock signal. The signals are conducted to the blocks of elastic buffersEB & CTRL 54, 55, where also the selected clock signal CLK to bereceived is conducted in order to synchronise the data. From the blocks54, 55, the data signals D1, D2 are conducted, by the data signalmultiplexer DATA MUX 56, as a signal D to the decoding block 57. In thedecoding block 57, the multiplexer 56 is controlled by the signal SYNC.

FIG. 6 illustrates a clock signal multiplexer according to a preferredembodiment of the invention, which multiplexer waits for a suitableclock signal phase in order to change the signals, whereafter thesignals are changed. The block 61 detecting the signal pattern “11”sends an active signal when the value of both clock signals CLK1, CLK2is one. The D-flip-flop circuits 62, 63, 64 form a phase shift sensitivecoupling, the outputs whereof are conducted to the block 65 detectingthe signal patterns “01” and “10”. Owing to said coupling, the output ofthe block 65 is raised to value one after a period of one clock cycle ofthe clock signal CLK2 has passed from the moment when the polarity ofthe phase difference between the clock signals CLK1, CLK2 was changed.Thus the phase difference at the moment of a rise in the output of theblock 65 is virtually non-existent or 180°. If the signals are cophasal,they can be exchanged almost without a phase shift after a short delayDL 66. The changing of the clock signals by the multiplexer 68 iscontrolled by the block 67 checking the criteria of the changeoveroperation, which block 67 receives as input signals a control signalrequesting the changeover, a signal indicating the clock signal pattern“11” and a signal indicating the shift in the clock signal phase anddelayed by the delay DL. On the basis of said criteria it is known thatthe signals are cophasal and not in a phase shift of 180°. The purposeof the delay DL is to ensure that the changing of the clock signals iscarried out while the clock signals are, from the point of view of thesystem, in a static mode, i.e. in mode one. This prevents the creationof a disturbing voltage peak.

FIG. 7 illustrates another clock signal changeover device according tothe invention, which device comprises, in addition to the embodimentillustrated in FIG. 6, an analog phase-locked loop (APLL) 71 forsynchronising the change, said loop multiplying the frequency of thesecond clock signal CLK2 by four. The output of the loop 71 is conductedto the block 67 that checks the changeover criteria. Owing to the use ofthe APLL, the delay DL illustrated in FIG. 6 is not needed here, becausethe changeover mode can be delayed by applying a later phase of thesignal that was multiplied by four in frequency.

The block 61 indicating the clock signal pattern “11” can be realisedfor example by an AND gate. The block 65 indicating the pattern “01” or“10” can be realised for instance by an XOR gate. The block 86indicating the pattern “10” can be realised for example by an inverterplus an AND gate.

FIG. 8 illustrates a third clock signal changeover device according tothe invention, wherein the phase difference between the signals isdetected while the prevailing time difference is no longer than thedelay DL. When the clock signal CLK1 is a little bit ahead of the clocksignal CLK2, the output mode of the D-flip-flops 81, 82 is transmittedas one, but when the phase difference in any case causes a delay DL 83,the output mode of the D-flip-flops 84, 85 is transmitted as zero. Nowthe signals are considered to be sufficiently accurately cophasal, andthe phase detector 86 obtains as input the output signals of theD-flip-flops 82, 85 in modes one and zero, and gives as output thesignal one. The analog phase locked loop 71, the block 67 for checkingthe changeover criteria and the multiplexer 68 are otherwise operated insimilar fashion as in the case of FIGS. 6 and 7, but the block 67 onlytakes into account the loop 71, the phase detector 86 and the controlsignals.

The respective elements in the above described drawings 6, 7 and 8 arereferred to by the same numbers in order to better illustrate thesituation.

Let us now observe an example of a propagation assured radio linkaccording to the invention, where the applied error correction method isan RS (63, 59) algorithm.

With both transmission paths in the outdoor units OU1, OU2, there iscalculated a check sum for a data flow of the length of the period underobservation, by multiplying the data RS (63, 59) to be checked by aprimitive polynome. The check sum is added as a continuation to the datato be checked. Here the period of observation is 354 bits, i.e. 59bytes, when one byte includes 6 bits. The length of the data frameformed by the payload information contained by said period plus thecheck sum is 378 bits, i.e. 63 bytes, of which the share of the checksum is 4 bytes.

Here the created data frames are transmitted via two different radiopaths, which are susceptible to disturbances in ways that are asdifferent as possible. Thus possible interference generally causeserrors only in one transmission path at a time.

The received data frames are treated in receiving outdoor units OU1, OU2by dividing the transmitted data frame by a generator polynome, so thata divisional remainder is obtained. The algorithm that locates errorsuses said remainder for detecting errors. In addition to errordetection, errors can also be corrected, in this case no more than twoerroneous bytes. The maximum amount of bytes that can be corrected canbe raised, by means of interleaving, up to eight bytes. The bytes arecorrected, and there is calculated an error sum that indicates how manyerrors the received data contained. In the outdoor units OU1, OU2 thereis created a data frame that contains the corrected payload informationand the error sum.

The indoor unit IU receives from both outdoor units OU1, OU2 a dataframe, and the changeover device CD selects, on the basis of the errorsum, a better transmission path for the payload information to befurther conducted to the output cable.

The invention can be used for example for backing up the links in radionetworks conforming to the plesiochronous digital hierarchy (PDH). Inthat case, for instance the frequencies of radio links in the GSMnetwork fluctuate within the range 7–38 GHz, and even a reading as highas 58 GHz is possible. In this type of application, the payload signalis a data signal of the plesiochronous digital hierarchy (PDH), with ageneral velocity of 2 Mbit/s or an even multiple thereof, but it mayalso be at least 34 Mbit/s. The length of the link is something betweena hundred meters up to as much as several tens of kilometers.

Here an active mode of the signal means that the signal criteria arefulfilled. Thus the signal mode is true or advantageously one. Thesignal modes can also be inverted, in which case instead of mode “11”,there is observed mode “00”. The term ‘identical modes’ refers, however,to modes “11” or “00”, and ‘un-identical modes’ means modes “01” or“10”.

The indoor unit and outdoor unit here refer to the symbolic position ofthe unit in the system, and it does not restrict the location of saidunit in the interior or exterior of a building.

Then number of transmission paths can be two or more.

The invention is not restricted to the above described embodiments only,but many modifications are possible within the scope of the inventiveidea defined in the appended claims.

1. A method for selecting a clock signal from a plurality of parallelclock signals received from a plurality of parallel transmission pathsin a digital data transmission, comprising the steps of: receiving, at aunit comprising a changeover device, parallel clock signals from atleast two parallel transmission paths, the parallel clock signals beinggenerated from a single originating signal, a first clock signal of theparallel clock signals being designated the selected clock signal andbeing transmitted to an output of the unit; requesting, by thechangeover device, a change of the selected clock signal from the firstclock signal to a second clock signal of the parallel clock signalsbased on an indication received from a phase locked loop of anunreliability in locking the first clock signal; determining whether thefirst and second clock signals are both in a predetermined mode anddetermining whether a polarity of a signal phase difference of the firstand second clock signals is inverted, thereby indicating the same phaseor a phase shift of 180°; generating a first signal when it isdetermined that the first and second clock signals are in thepredetermined mode, initiating a time delay when it is determined thatthe polarity of the signal phase difference of the first and secondclock signals is inverted, and generating a second signal after the timedelay has elapsed; and changing the selected clock signal to the secondclock signal in response to said step of requesting and when said firstand second signals are present, whereby said step of changing occursproximate a phase coincidence of the first and second clock signals. 2.The method of claim 1, wherein said step of requesting comprisesrequesting the changing of the selected clock signal using a controlsignal generated by the changeover device, the control signal beingbased on the indication of said unreliability of the locking of thefirst clock signal by said phase locked loop; and wherein said step ofchanging comprises regulating a multiplexer to change the clock signalswhen the control signal, the first signal, and the second signal arepresent.
 3. A unit for digital data transmission and for changingparallel clock signals in the digital data transmission, comprising: achangeover device including means for receiving parallel clock signalsfrom at least two parallel data transmission paths, the parallel clocksignals being generated from a single originating clock signal; meansfor forwarding a selected one of the parallel clock signals to an outputof the unit; and means for changing a selected clock signal from a firstclock signal of the parallel clock signals to a second clock signal ofthe parallel clock signals based on an indication of unreliability oflocking the selected clock signal; means for detecting whether the firstand second clock signals are in an identical mode and that a polarity ofa signal phase difference is inverted; wherein the change of theselected clock signal occurs after a delay to ensure that the changeoveroccurs while the clock signals are static.
 4. The unit of claim 3,wherein said changeover device comprises an application specificintegrated circuit including: a clock signal multiplexer having meansfor determining when a suitable clock signal phase is present and meansfor performing the change of the selected clock signal when the suitableclock signal phase is present; at least two data frame decoding blocksfor respectively receiving the parallel clock signals and associateddata signals from the at least two data transmission paths and formingdecoded control signals and data signals therefrom; at least two elasticbuffer and control blocks receiving the decoded control signals anddecoded data signals and forming data signals that are synchronized bythe selected clock signal; a data signal multiplexer selecting the datasignal to be received; and a further decoding block synchronizing thereceived data signal using the selected clock signal into a final datasignal and controlling the data signal multiplexer using a synchronizingsignal generated by said at least two data frame decoding blocks.
 5. Theunit of claim 3, wherein the unit is part of a radio link in a mobiletelecommunications system.
 6. An arrangement for digital datatransmission, comprising: a first indoor unit for dividing a clocksignal to be transmitted into parallel clock signals; a second indoorunit for receiving the parallel clock signals, selecting one of theparallel clock signals as a selected clock signal, and transmitting theselected clock signal to an output of the second indoor unit; a firstchangeover device in said first indoor unit and a second changeoverdevice in said second indoor unit for receiving the parallel clocksignals; and first and second outdoor units each provided with atransmitter for transmitting one of the parallel clock signals to bechanged and respectively a receiver for receiving a parallel clocksignal, and a phase locked loop synchronized with the selected clocksignal, said second changeover device generating a request for changingthe selected clock signal from a first clock signal to a second clocksignal of the parallel clock signals based on an indication of anunreliability in locking the selected clock signal with the phase lock.7. The arrangement of claim 6, wherein each of said first and secondchangeover devices is realized in an application specific integratedcircuit which comprises: a clock signal multiplexer having means fordetermining when a suitable clock signal phase is present and means forperforming the changeover when the suitable clock signal phase ispresent; at least two data frame decoding blocks for respectivelyreceiving the parallel clock signals and associated data signals fromthe at least two data transmission paths and forming decoded controlsignals and data signals therefrom; at least two elastic buffer andcontrol blocks respectively receiving the decoded control signals anddecoded data signals and forming data signals that are synchronized bythe selected clock signal; a data signal multiplexer selecting the datasignal to be received; and a further decoding block synchronizing thereceived data signal using the selected clock signal into a final datasignal and controlling the data signal multiplexer using a controlsignal generated by said at least two data frame decoding blocks.
 8. Thearrangement of claim 7, wherein the control signal includes asynchronizing signal, a bit error signal, a frame alignment alarmsignal, and a pseudo frame signal.
 9. The arrangement of claim 7,wherein said clock signal multiplexer comprises: a first block fordetecting identical modes of the parallel clock signals, said firstblock generating an active signal when the parallel clock signals are inthe same mode; D-flip-flop circuits forming a phase shift sensitivecoupling; a second block for detecting un-identical modes of the clocksignals connected to outputs of the phase shift sensitive coupling, anoutput of said second block being raised, in response to said phaseshift sensitive coupling, to the value one after a period of one cycleof the second parallel clock signal has passed from the moment when thepolarity of the phase difference between the parallel clock signals waschanged; a delay circuit for delaying the output signal from said secondblock; a third block checking for the request for changing the selectedclock signal, the output signal from the first block, and the delayedoutput signal from the second block; and a multiplexer for changing theselected clock signal from the first clock signal to the second clocksignal under the control of said third block when the request forchange, the output signal from the first block, and the delayed outputsignal from the second block are present at the third block.
 10. Achangeover device for selecting a clock signal from a plurality ofparallel clock signals, comprising: means for receiving parallel clocksignals from at least two data transmission paths, the parallel clocksignals being generated from a single originating clock signal, and aselected clock signal from the parallel clock signals; means forreceiving a control signal indicating an unreliability of locking theselected clock signal; change requirement means for determining a changein the selected clock signal is required from a first clock signal to asecond clock signal in response to the control signal; same mode meansfor determining that the first and second clock signals are in the samemode; inversion means for determining an inversion of the polarity of asignal phase difference between the first and second clock signalsindicating a situation, thereby indicating that the first and secondsignals were either in the same phase or in a phase shift of 180°; andcontrol means for checking said change requirement means, said same modemeans, and said inversion means, initiating a time delay when arequirement for a change is determined, the first and second clocksignals are in the same mode, and the inversion is determined, andperforming the changeover after the time delay is elapsed to ensure thatthe changeover is effected while the clock signals are in a static mode.11. An application specific integrated circuit, comprising: means forreceiving parallel clock signals from at least two data transmissionpaths, the parallel clock signals being generated from a signaloriginating clock signal, and a selected clock signal from the parallelclock signals; means for receiving a control signal indicating anunreliability of locking the selected clock signal; change requirementmeans for determining a change in the selected clock signal is requiredfrom a first clock signal to a second clock signal in response to thecontrol signal; same mode means for determining that the first andsecond clock signals are in the same mode; inversion means fordetermining an inversion of the polarity of a signal phase differencebetween the first and second clock signals indicating a situation,thereby indicating that the first and second signals were either in thesame phase or in a phase shift of 180°; and control means for checkingsaid change requirement means, said same mode means, and said inversionmeans, initiating a time delay when a requirement for a change isdetermined, the first and second clock signals are in the same mode, andthe inversion is determined, and performing the changeover after thetime delay is elapsed to ensure that the changeover is effected whilethe clock signals are in a static mode.
 12. A clock multiplexer,comprising: means for receiving first and second parallel clock signalsfrom two data transmission paths, the first and second parallel clocksignals being generated from a signal originating clock signal, saidfirst parallel clock signal being a selected clock signal; a first blockgenerating an active signal when the parallel clock signals are in thesame mode; D-flip-flop circuits forming a phase shift sensitivecoupling; a second block detecting un-identical modes of the clocksignals connected to outputs of the phase shift sensitive coupling, anoutput of said second block being raised, in response to said phaseshift sensitive coupling, to the value one after a period of one cycleof the second parallel clock signal has passed from a point in time whena polarity of a phase difference between the parallel clock signals waschanged; a delay circuit for delaying the output signal from said secondblock; a third block checking for the request for changing the selectedclock signal, the output signal from the first block, and the delayedoutput signal from the second block; and a multiplexer for changing theselected clock signal from the first clock signal to the second clocksignal under the control of said third block when the request forchange, the output signal from the first block, and the delayed outputsignal from the second block are present at the third block.
 13. Anapplication specific integrated circuit, comprising: means for receivingfirst and second parallel clock signals from two data transmissionpaths, the first and second parallel clock signals being generated froma signal originating clock signal, said first parallel clock signalbeing a selected clock signal; a first block generating an active signalwhen the parallel clock signals are in the same mode; D-flip-flopcircuits forming a phase shift sensitive coupling; a second blockdetecting un-identical modes of the clock signals connected to outputsof the phase shift sensitive coupling, an output of said second blockbeing raised, in response to said phase shift sensitive coupling, to thevalue one after a period of one cycle of the second parallel clocksignal has passed from a point in time when a polarity of a phasedifference between the parallel clock signals was changed; a delaycircuit for delaying the output signal form said second block; a thirdblock checking for the request for changing the selected clock signal,the output signal from the first block, and the delayed output signalfrom the second block; and a multiplexer for changing the selected clocksignal from the first clock signal to the second clock signal under thecontrol of said third block when the request for change, the outputsignal from the first block, and the delayed output signal from thesecond block are present at the third block.